NUPUR NAVLAKHA

Postdoctoral Fellow

The University of Texas at Austin

Nupur Navlakha is a Postdoctoral Fellow under Prof. Sanjay Banerjee in the Department of Electrical & Computer Engineering at The University of Texas at Austin, United States. Her research focuses on computation design of novel devices and materials, device physics & modeling. Currently, she is investigating material systems for low power applications. She completed her Ph.D. from the Department of Electrical Engineering at Indian Institute of Technology (IIT) Indore, India, in 2018 under supervision of Dr. Abhinav Kranti. Her work involved assessment of MOS transistors for low power capacitorless dynamic memory. She has been mentoring undergraduates and graduates, has served as a reviewer for ten esteemed journals and is recognized as a golden reviewer in reputed journals. She has published 34 papers in peerreviewed journals and conferences and has filed an Indian patent for innovating a tunnel FET design for enhanced performance of capacitorless dynamic memory.

Low Power Tunneling based Transistors for Capacitorless Dynamic Memory Applications

With the advent of Moore’s law and Dennard’s scaling theory, the performance of processor units in computers improved. However, the overall system performance, which is based on the interaction between the processor and memory units, didn’t improve with the same pace due to the lack of focus on memory. Thus, the emphasis has been directed to enhance the speed and density of memory with operation at low power. This necessitated reduction in the size of the capacitor in the conventional Dynamic Random Access Memory (DRAM) based on one transistor and capacitor (1T-1C). The problem was circumvented with the introduction of the single transistor (also referred as 1T) as DRAM cell. Thus, my work focuses on an energy efficient device, Tunnel Field Effect Transistor (TFET) as 1T-DRAM. The key contribution is to provide insights into the physical phenomenon occurring in the device, which influences the operation of TFET as DRAM through device design and material engineering. The systematic analysis through innovative approaches leads to capacity, retention, at low energy with operation at reduced size. The use of an energy optimized DRAM memory with RT > 64 ms is wellsuited for standalone applications, and as well as, for integrated circuits embedded with logic devices.